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geda:design_flow_and_hierarchy_roadmap [2012/02/20 15:14]
127.0.0.1 external edit
geda:design_flow_and_hierarchy_roadmap [2015/07/25 15:30] (current)
jt_eaton [Required for production circuits]
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 ====== Required for production circuits ====== ====== Required for production circuits ======
   * hierarchy in schematic and netlist and pcb -- modules that can be reused, arrayed.   * hierarchy in schematic and netlist and pcb -- modules that can be reused, arrayed.
 +    The classic example of this is a stereo amplifier. You enter the schematic of an amplifier channel and a second one showing controls and power. You enter a symbol for the unit that points to three schematic pages. ​       
 +    Page 1 is the control/​power , Page 2 is the amplifier with macro substitutions of right and U100 for all nets and Refdes, Page 3 is the amplifier with macro substitutions of left and U200 for all nets and Refdes. 
 +     
 +     
 +    Extra credit if the number of channels is controlled by an attribute set when you instantiate the unit symbol. This is comparable to the verilog generate command.
 ===== intermediate translation file format VHDL? EDIF?  ===== ===== intermediate translation file format VHDL? EDIF?  =====
 === Schematic, Layout, logic sim, analog sim, etc === === Schematic, Layout, logic sim, analog sim, etc ===
geda/design_flow_and_hierarchy_roadmap.txt · Last modified: 2015/07/25 15:30 by jt_eaton