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====== Gnetlist ======





====== Bill of Materials (BOM) Generation ======
There are five different backends for [[http://geda.seul.org/tools/gnetlist/index.html|gnetlist]] which enable you to export a BOM. Call them with -g and be sure to give the output file name with the -o option:
<code>
   gnetlist -g partslist3 -o output.bom schematic.sch 
</code> 

gnetlist descends into sub sheets and list the contents of these schematics along with the parts from the top document. 

The backends bom and bom2 require read access to a local file called attribs. This file should contain the name of the attributes to be listed each in a seperate line. E.g:
<code>
value
footprint
description
</code>

Each of the backends lists and sorts the parts in different ways in an ascii file. Choose the one you like best:

=== bom ===
The bom backend needs to read an attribs file (see above). The list produced by "-g bom" will contain as many lines as there are components. Columns are seperated by tab characters. Lines are not sorted.

=== bom2 === 
The bom2 backend also needs to read an attribs file. With "-g bom2" the refdeses of all components with the same value will be collected into a single line. Columns are seperated by colons. Different items in the same column are seperated by a komma character.

=== partslist1 ===
A list produced by the partlist1 backend gives a line for each and every component. Lines are sorted alphabetically by refdes. Columns are "refdes", "device", "value", "footprint" and "quantity". Since every line contains just one part, the quantity is always "1".

=== partslist2 ===
This backend produces output similar to partslist1. Lines are sorted by the value of the device attribute.

=== partslist3 ===
The backend partslist3 assembles all parts with the same value in a single line, very much like bom2. Lines are sorted by the value of the device attribute. The fourth column reports the number of parts in a line. Columns are seperated by the tab character, items by space.

====== Design Rule Check (DRC) ======
===== How do I check my schematics? =====
You can check your schematics using the drc2 gnetlist’s backend. It will check your schematics for some common errors, like duplicate references, unconnected pins, unused slots and more.

Run the drc2 backend with the following command:
<code>gnetlist -g drc2 -o MyDesign.drc MyDesign.sch</code>

With this command, the DRC output is written into the file “MyDesign.drc”. You can then view this file with a text editor and see the DRC warnings and errors.

===== How do I see the DRC output in the screen, without writing to a file? =====
Run the drc2 backend with the following command:
<code>gnetlist -g drc2 -o - MyDesign.sch</code>

This way, you will see the DRC output directly in your screen.

===== I want to disable some of the schematic DRC checks. How can I do it? =====
The drc2 backend is highly configurable. You have to put some special commands into a file and use the “-l” option of gnetlist with it.

The most common commands are:
  * (define dont-check-non-numbered-parts 1) ;; Disable the non-numbered parts check
  * (define dont-check-duplicated-references 1) ;; Disable the duplicate references check
  * (define dont-check-one-connection-nets 1) ;; Disable the check for nets with only one connection.
  * (define dont-check-pintypes-of-nets 1) ;; Disable the pintype check
  * (define dont-check-not-driven-nets 1) ;; Disable the driven net check
  * (define dont-check-unconnected-pins 1) ;; Disable the unconnected pins check
  * (define dont-check-duplicated-slots 1) ;; Disable the duplicated slots check
  * (define dont-check-unused-slots 1) ;; Disable the unused slots check
  * (define dont-check-slots 1) ;; Disable slot number check
  * (define action-unused-slots #\w) ;; Output an unused slots as a warning
  * (define action-unused-slots #\e) ;; Output an unused slots as an error
  * (define action-unused-slots #\c) ;; An unused slot is OK.
  * (define case_insensitive 1) ;; Do all checks case insensitive

There are some other advanced commands, to modify the DRC matrix and the pintype which can drive a net. See the backend file “gnet-drc2.scm” with a text editor. At the beginning there is the available documentation.

Copy the above lines you want into a file (for example “drc_rules.txt”), one per line, and run the drc checker:
<code>gnetlist -g drc2 -l drc_rules.txt -o MyDesign.drc MyDesign.sch</code>

With this command, the DRC output is written into the file “MyDesign.drc”. You can then view this file with a text editor and see the DRC warnings and errors.

===== Can I include the DRC checking into a Makefile and stop when errors or warnings are found? =====
Yes. The drc2 backend will return an error if there are errors or warnings, so you can add the following to your Makefile:
<code>$(objects).drc : $(objects).sch
          gnetlist -g drc2 $(objects).sch -o $(objects).drc</code>

If you are going to simulate your design, then you can add the following to your Makefile:
<code>$(objects).cir : $(objects).sch $(objects).drc
          grep -v ERROR $(objects).drc >/dev/null 2>&1
          gnetlist -g spice-sdb $(objects).sch  -o $(objects).cir</code>

If not, please use the above example and adapt it to your own workflow.

===== There are some warnings in my design I'm aware of. Can I ignore the warnings in the return value? =====
Use the “-O ignore-warnings-in-return-value” option:
<code>gnetlist -g drc2 -o - MyDesign.sch -O ignore-warnings-in-return-value</code>

Do this with caution! You will be missing all the warnings!
====== Gnetlist build/run-time problems ======

===== I get a "parenthesis mismatch" error when running gnetlist.  What's up? =====

Starting with Fedorea Core 6 and SuSE 10.2, many users have reported an error which looks like this:

<code>
$gnetlist -g spice-sdb -o TwoStageAmp.cir TwoStageAmp.sch
Command line passed = gnetlist -g spice-sdb -o TwoStageAmp.cir TwoStageAmp.sch
gEDA/gnetlist version 20061020
gEDA/gnetlist comes with ABSOLUTELY NO WARRANTY; see COPYING for more details.
This is free software, and you are welcome to redistribute it under certain
conditions; please see the COPYING file for more details.

Remember to check that your schematic has no errors using the drc2 backend.
You can do it running 'gnetlist -g drc2 your_schematic.sch -o drc_output.txt'
and seeing the contents of the file drc_output.txt.

Loading schematic [/home/nano/TwoStageAmp/TwoStageAmp.sch]
Probably parenthesis mismatch in /usr/share/gEDA/scheme/gnet-spice-sdb.scm
Most recently read form: (#@begin #<unspecified>)
ERROR: Unbound variable: spice-sdb
</code>

Several gnetlist backends evince this problem, including spice-sdb and drc2.

This is a bug in guile-1.8.X.  The gEDA developers are working on a fix.  Meanwhile, try to backrev your version of guile to 1.6.7, which is known to work flawlessly with gEDA.

===== The gnetlist bom backend does not work. What is wrong? =====
If when running gnetlist like this:
<code>gnetlist -g bom filename.sch</code>

and gnetlist outputs an error message like:
<code>Loading schematic [filename.sch]
ERROR: In procedure open-file:
ERROR: No such file or directory: “attribs”</code>

then you need to create a file called “attribs” in the current directory which contains the attributes which you want inside the bom file. An example of this file would be:
<code>device
value</code>

For information about BOM generation see [[#Bill of Materials (BOM) Generation|above]].

===== Some gnetlist backends overflow the stack. How do I solve this? =====
If you get an error message like:
<code>ERROR: Stack overflow</code>

when running certain larger sized schematics through some of the backends, then add the following to a **''~/.gEDA/gnetlistrc''** or a local **''gnetlistrc''** (in the current working directory):
<code>(debug-options (list 'stack 200000))
(eval-options (list 'stack 200000))</code>

If this does not work, then edit the appropriate backend (usually named: gnet-backend_name.scm) and put the above lines at the top of this file. The gnetlist backends can be found in **''${prefix}/share/gEDA/scheme''**. Also send an e-mail to geda-user reminding the developers to fix this. Remember, you must subscribe to geda-user before you can post to the list.

===== gnetlist has created a netlist with duplicate pins!? =====
There has been at least one report of the following message coming from PCB after loading up a netlist created by gnetlist:
<code>28: Error! Element R117 pin 2 appears multiple times in the netlist file.
29: Error! Element C167 pin 2 appears multiple times in the netlist file.</code>

What has happened is gnetlist (really libgeda) created two nets instead of one. This happens when you draw two nets that cross each other and a pin connecting to the intersection of the two crossing nets. Note the cross nets are not connected together. A schematic which demonstrates this looks like this:

{{:geda:ambiguous1.png}}

The developers are debating whether or not this is a bug in gnetlist, but for now make sure your net connections, especially those that involve pins connecting to the middle of other nets, are explicitly drawn. Here is how the above connection should be drawn to netlist properly:

{{:geda:ambiguous1_fixed.png}}
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