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geda:glossary [2012/02/22 18:48]
kokr gpleda -> geda-project
geda:glossary [2014/04/18 08:20]
vzh Add links to translations
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 +//​Translations of this page are also available in the following languages://​ [[glossary.fr|Français]],​ [[glossary.ru|Русский]].
 +
 ====== Glossary of gEDA (and EDA) terms ====== ====== Glossary of gEDA (and EDA) terms ======
  
 The design of electronics involves a host of specific terms. Some words have a meaning that only vaguely resembles the use in everyday life. This glossary aims to be a dictionary of terms specific to the gEDA suite, as well as to the larger world of CAD for electronics. Unfortunately,​ there is no universal naming scheme for concepts in the area of electronic design. The glossary will give hints on how things are called in other design suites. The design of electronics involves a host of specific terms. Some words have a meaning that only vaguely resembles the use in everyday life. This glossary aims to be a dictionary of terms specific to the gEDA suite, as well as to the larger world of CAD for electronics. Unfortunately,​ there is no universal naming scheme for concepts in the area of electronic design. The glossary will give hints on how things are called in other design suites.
  
-!!(Wiki-authors:​ Please insert new terms according to the alphabet)!!+<note important> ​(Wiki-authors:​ Please insert new terms according to the alphabet) ​</​note>​
   * **action**: In pcb, an action is an internal command. Actions can be triggered via the GUI or via the command line interface. A sequence of assembled in a file can be executed on start-up of the application.   * **action**: In pcb, an action is an internal command. Actions can be triggered via the GUI or via the command line interface. A sequence of assembled in a file can be executed on start-up of the application.
   * **annular ring**: The annular ring, sometimes also called **annulus**,​ is a diameter of copper that needs to be placed arround metalized holes like pads and vias. The minimum size of the annular ring is specified by the pcb-fab. A common requirements is 16 mil larger than the hole.   * **annular ring**: The annular ring, sometimes also called **annulus**,​ is a diameter of copper that needs to be placed arround metalized holes like pads and vias. The minimum size of the annular ring is specified by the pcb-fab. A common requirements is 16 mil larger than the hole.
-  * **dead copper**: A part of the copper layer which is not connected to any net defined in the netlist. By definition, this may be any object pcb defines. However, the term commonly refers to unconnected snippets of a polygon which is divided by a track. ​+  * **dead copper**: A part of the copper layer which is not connected to any net defined in the netlist. By definition, this may be any object pcb defines. However, the term commonly refers to unconnected snippets of a polygon which is divided by a track.
   * **design flow**: The order or stages through which you take your design as you progress from initial concept, through schematic capture, attribute attachment, netlisting, and layout. The gEDA Suite uses entirely separate programs for different stages of the flow; each tool in the suite reads the output file produced by the previous tool, and writes a file to be read by the next tool in the flow. The gEDA design flow for designing a PCB is illustrated [[geda:​usage#​what_does_the_design_flow_in_geda_look_like|here]]. Note that the design flow for different tasks might look different. For example, if your goal is to simulate your circuit, you will use a different flow than that shown in the link above.   * **design flow**: The order or stages through which you take your design as you progress from initial concept, through schematic capture, attribute attachment, netlisting, and layout. The gEDA Suite uses entirely separate programs for different stages of the flow; each tool in the suite reads the output file produced by the previous tool, and writes a file to be read by the next tool in the flow. The gEDA design flow for designing a PCB is illustrated [[geda:​usage#​what_does_the_design_flow_in_geda_look_like|here]]. Note that the design flow for different tasks might look different. For example, if your goal is to simulate your circuit, you will use a different flow than that shown in the link above.
-  * **flag**: Objects can contain a number of flags. These indicate specific properties of the object. Examples are the ''​square''​ flag for angular pads, or the ''​onsolder''​ flag for objects on the other side of the board. ​ +  * **flag**: Objects can contain a number of flags. These indicate specific properties of the object. Examples are the ''​square''​ flag for angular pads, or the ''​onsolder''​ flag for objects on the other side of the board.
   * **footprint**:​ The pattern of metal and silkscreen which defines where you place a component on a PCB. Footprints are the placed by the user onto the PC board during the “placement” phase of PCB layout (using e.g. the open-source tool PCB). A footprint is also sometimes called called a “decal” (PADS), or a “land-pattern”.   * **footprint**:​ The pattern of metal and silkscreen which defines where you place a component on a PCB. Footprints are the placed by the user onto the PC board during the “placement” phase of PCB layout (using e.g. the open-source tool PCB). A footprint is also sometimes called called a “decal” (PADS), or a “land-pattern”.
   * **gedasymbols.org**:​ A website dedicated to present symbols, footprints, scripts, plug-ins and other stuff users contributed to the geda project. Contributions can be accessed by mouse click. The whole site can be downloaded via concurrent versions system ([[wp>​Concurrent_Versions_System|CVS]]). This also the way users maintain their page on the site. See, [[http://​gedasymbols.org|http://​gedasymbols.org]].   * **gedasymbols.org**:​ A website dedicated to present symbols, footprints, scripts, plug-ins and other stuff users contributed to the geda project. Contributions can be accessed by mouse click. The whole site can be downloaded via concurrent versions system ([[wp>​Concurrent_Versions_System|CVS]]). This also the way users maintain their page on the site. See, [[http://​gedasymbols.org|http://​gedasymbols.org]].
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   * **rats nest**: The lines drawn on the pcb working area that hint which pads still need to be connected with tracks. Unlike the actual tracks the rats nest are straight lines. If multiple pads are involved in a net, pcb tries to draw rats nests with the shortest possible length.   * **rats nest**: The lines drawn on the pcb working area that hint which pads still need to be connected with tracks. Unlike the actual tracks the rats nest are straight lines. If multiple pads are involved in a net, pcb tries to draw rats nests with the shortest possible length.
   * **refdes**: Short for [[wp>​reference designator]]. The unique designator (or name) of a component. The gEDA tools rely on the refdefs to organize the components internally. Therefore, for successful creation of a printed circuit board every component has to be linked with a refdes. Usually, the refdes consists of a few upper case letters and a digit. Examples: R1, R2, U115, CONN3. (Protel: “Designator”)   * **refdes**: Short for [[wp>​reference designator]]. The unique designator (or name) of a component. The gEDA tools rely on the refdefs to organize the components internally. Therefore, for successful creation of a printed circuit board every component has to be linked with a refdes. Usually, the refdes consists of a few upper case letters and a digit. Examples: R1, R2, U115, CONN3. (Protel: “Designator”)
-  * **silkscreen**:​ This is the layer that defines the text and graphics printed on the pcb board. It usually contains the name of the board, outlines of the components and possibly their values or refdes. The origin of the name is the silk traditionally used during the print process. ​+  * **silkscreen**:​ This is the layer that defines the text and graphics printed on the pcb board. It usually contains the name of the board, outlines of the components and possibly their values or refdes. The origin of the name is the silk traditionally used during the print process.
   * **slot**: Some components contain multiple, identical devices inside a single package. The IOs for each component are mapped to different pin sets on the package. A classic example is the TTL 7400 quad nand gate. Gschem (like other schematic capture packages) handles this type of component by allowing you to draw four separate nand gate symbols, and then selecting which **slot** each symbol should have by attaching a slot attribute to the symbol. In the example of the 7400 quad nand, you would select **''​slot=1''​** for the first appearance of the symbol, slot=2 for the second appearance, and so on. Note that in gschem you need to attach power nets to a slotted component only **once**. (Other schematic capture programs like Orcad require you to attach common nets – like power nets – on each instantiation of the slotted symbol.)   * **slot**: Some components contain multiple, identical devices inside a single package. The IOs for each component are mapped to different pin sets on the package. A classic example is the TTL 7400 quad nand gate. Gschem (like other schematic capture packages) handles this type of component by allowing you to draw four separate nand gate symbols, and then selecting which **slot** each symbol should have by attaching a slot attribute to the symbol. In the example of the 7400 quad nand, you would select **''​slot=1''​** for the first appearance of the symbol, slot=2 for the second appearance, and so on. Note that in gschem you need to attach power nets to a slotted component only **once**. (Other schematic capture programs like Orcad require you to attach common nets – like power nets – on each instantiation of the slotted symbol.)
   * **solder layer**: This is the side of the board where traditional,​ thru hole components are soldered. (Protel: “Bottom Layer”)   * **solder layer**: This is the side of the board where traditional,​ thru hole components are soldered. (Protel: “Bottom Layer”)
geda/glossary.txt · Last modified: 2014/04/25 02:52 by vzh