geda:hierarchy
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geda:hierarchy [2015/03/28 17:02] rlutz More work on the page |
geda:hierarchy [2016/02/29 09:42] rlutz add missing pieces |
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| - | //(This page is still incomplete.)// | ||
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| ====== Hierarchical schematics ====== | ====== Hierarchical schematics ====== | ||
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| In ''gschem'', you can navigate the schematic hierarchy using the commands from the “Hierarchy” menu. To view the underlying schematic for a subcircuit component, select it and use **Hierarchy→Down Schematic**. Once finished editing, use **Hierarchy→Up** to return to the original schematic. (This works only if you accessed the subcircuit's schematic in that way.) Analogously, you can edit the subcircuit symbol itself using **Hierarchy→Down Symbol**. | In ''gschem'', you can navigate the schematic hierarchy using the commands from the “Hierarchy” menu. To view the underlying schematic for a subcircuit component, select it and use **Hierarchy→Down Schematic**. Once finished editing, use **Hierarchy→Up** to return to the original schematic. (This works only if you accessed the subcircuit's schematic in that way.) Analogously, you can edit the subcircuit symbol itself using **Hierarchy→Down Symbol**. | ||
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| + | As an alternative to using the same net name, you can add pins to a subsheet symbol to route nets to and from that schematic. See the section //Input/output pins// below for details. | ||
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| + | ===== Hierarchy as a grouping/instantiation mechanism ===== | ||
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| + | If you want to include a subcircuit multiple times in your schematic, you need a way to tell the components of one instantiation from those of another one (given that your subcircuit contains any components). This is where refdef mangling comes in. You enable it by specifying | ||
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| + | (hierarchy-uref-mangle "enabled") | ||
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| + | in ''gnetlistrc''. Now, ''gnetlist'' constructs the name of an instantiated component by appending it to the subsheet symbol's ''refdes='' attribute, separated by a slash. You can configure this in ''gnetlistrc''. For example, to list the component ''refdes='' first and use a colon as a separator, use | ||
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| + | (hierarchy-uref-order "prepend") | ||
| + | (hierarchy-uref-separator ":") | ||
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| + | Named nets from one instantiation will connect to the same net of another one. This means you can't use net names to connect (non-power) pins across the hierarchy any more; you need I/O pins instead. Also, you will probably want to use separate net namespaces so you don't short-circuit nets between instantiations when using net names. | ||
| ==== Input/output pins ==== | ==== Input/output pins ==== | ||
| - | As an alternative to using the same net name, you can add pins to a subsheet symbol to route nets to and from that schematic. For each pin on the symbol, you need to add a corresponding footprint-less I/O symbol to the subsheet whose ''refdes='' matches the ''pinlabel='' of the pin. (You can normally use the ''in-1.sym'' and ''out-1.sym'' symbols from the generic “Input/Output” symbol library for this.) | + | In order to connect a net to a subcircuit, you need to add a pin to the subcircuit symbol and a corresponding footprint-less I/O component to the subcircuit whose ''refdes='' matches the ''pinlabel='' of the pin. During netlist generation, these two nets will be connected. (You can normally use the ''in-1.sym'' and ''out-1.sym'' symbols from the generic “Input/Output” symbol library for this.) |
| <note important> | <note important> | ||
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| </note> | </note> | ||
| - | ===== Hierarchy as a grouping/instantiation mechanism ===== | + | ===== Separating net=/netname= namespaces ===== |
| - | If you want to include a subcircuit multiple times in your schematic, you need a way to tell the components of one instantiation from those of another one (given that your subcircuit contains any components). This is where uref mangling comes in. You enable it by specifying | + | The typical and cleanest way to use hierarchy is to enable both refdes and net=/netname= mangling. This means that the subcircuit lives in a namespace of its own, and the only way to connect nets between the instantiating and the instantiated schematic is through pins of the subsheet symbol and I/O ports in its schematic. If you want to include a subcircuit multiple times in your design, even though it's not strictly necessary, this is the recommended way to use hierarchy, as you would otherwise have to be very careful about avoiding naming nets in the subschematic which would cause them to be silently short-circuited between instantiations. |
| - | (hierarchy-uref-mangle "enabled") | + | You enable net=/netname= mangling it by specifying |
| - | in ''gnetlistrc''. Now, ''gnetlist'' constructs the name of an instantiated component by appending it to the subsheet symbol's ''refdes='' attribute, separated by a slash. You can configure this in ''gnetlistrc''. For example, to list the component ''refdes='' first and use a colon as a separator, use | + | (hierarchy-netattrib-mangle "enabled") |
| + | (hierarchy-netname-mangle "enabled") | ||
| - | (hierarchy-uref-order "prepend") | + | in ''gnetlistrc''. As with refdes mangling, you can also configure the way mangled net names are constructed. |
| - | (hierarchy-uref-separator ":") | + | |
| - | <note important> | + | ==== netname= mangling vs. net= mangling ==== |
| - | Named nets from one instantiation will connect to the same net of another one. If you are using net names in the subcircuit, you will probably want to use separate net namespaces to avoid that. | + | |
| - | </note> | + | |
| - | ===== Separating net=/netname= namespaces ===== | + | There are two slightly different options which influence net namespaces: ''netname='' mangling means that net names set via the ''netname='' attribute on nets are prefixed or suffixed with the subsheet instance's hierarchy tag. ''net='' attribute mangling means that net names which are set via the ''net='' attribute on components (like, for example, ''Vcc'' and ''GND'' pins in some libraries) are prefixed or suffixed with the subsheet instance's hierarchy tag. |
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| + | Usually, when using net namespaces, you would enable both ''netname='' and ''net='' mangling. Depending on how you use hierarchy in your design, there might be use cases where you might want to disable one of them, though: If you disable ''netname='' mangling, you gain the ability to use global net names and connect nets across the hierarchy by setting the ''netname='' attribute while still having implicit nets separate. If you disable ''net='' mangling, all implicit pins (usually power and ground pins) across all of your schematic pages will be connected, so you don't have to use explicit power and ground pins on your subsheet symbols. Both approaches come at the cost of reduced readability, though: you can't tell any more how a subsheet is connected to the rest of the design by just looking at the schematic. | ||
| - | … | ||
geda/hierarchy.txt · Last modified: 2016/02/29 09:42 by rlutz
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