Depending on what you want to achieve, there are several options how to use hierarchy. If you are unsure, ask yourself if you want to include a subcircuit multiple times in your design, or want to represent a subsheet as a symbol in another sheet. If you answer either with yes, go with full mangling. If not, you probably don't need hierarchy at all and can just use multiple schematic files.

If you just want to split your schematic to multiple pages, you don't need to use hierarchy at all. Just list the individual schematic files when invoking gnetlist:

$ gnetlist -g geda page-one.sch page-two.sch

If you are using the same netname= attribute on different pages, the nets will automatically be connected.

Alternatively, you can create a top schematic which contains symbols for each subsheet and tell gnetlist to go look for the corresponding schematic files. You do so by adding a source= attribute to the symbol and adding the directory which contains the subsheets to the source library. Usually this will be the same directory as the schematic containing the subsheet symbol, so add the following line to gnetlistrc (either your global one in ~/.gEDA/, or a project-specific one in the same directory):

(source-library ".")

You also need to tell gnetlist to disable component and net name mangling or you will end up with component names like U?/R1, and your nets will not connect. To do so, add the following lines to gnetlistrc:

(hierarchy-netattrib-mangle "disabled")
(hierarchy-netname-mangle "disabled")
(hierarchy-uref-mangle "disabled")

Now when invoking gnetlist, just specify the main schematic file:

$ gnetlist -g geda main.sch

As an alternative to using the same net name, you can add pins to a subsheet symbol to route nets to and from that schematic. For each pin on the symbol, you need to add a corresponding footprint-less I/O symbol to the subsheet whose refdes= matches the pinlabel= of the pin.

If you want to include a subcircuit multiple times in your schematic, you need a way to tell the components of one instantiation from those of another one (given that your subcircuit contains any components). This is where uref mangling comes in. You enable it by specifying

(hierarchy-uref-mangle "enabled")

in gnetlistrc. Now, gnetlist constructs the name of an instantiated component by appending it to the subsheet symbol's refdes= attribute, separated by a slash. You can configure this in gnetlistrc. For example, to list the component refdes= first and use a colon as a separator, use

(hierarchy-uref-order "prepend")
(hierarchy-uref-separator ":")

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