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geda:icarus_readme [2014/04/14 09:39]
rlutz Use wiki syntax (part 1)
geda:icarus_readme [2014/04/14 09:57] (current)
rlutz Use wiki syntax (part 2)
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 yet. It does currently handle a mix of structural and behavioral yet. It does currently handle a mix of structural and behavioral
 constructs. For a view of the current state of Icarus Verilog, see its constructs. For a view of the current state of Icarus Verilog, see its
-home page at <http://​www.icarus.com/​eda/​verilog>.+home page at http://​www.icarus.com/​eda/​verilog.
  
 Icarus Verilog is not aimed at being a simulator in the traditional Icarus Verilog is not aimed at being a simulator in the traditional
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 tools. tools.
  
-For instructions on how to run Icarus Verilog, see the ''​iverilog''​ [[icarus_mp|man page]].+For instructions on how to run Icarus Verilog, see the ''​[[icarus_mp|iverilog(1)]]''​ man page.
  
  
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  * **GNU Make**\\ The Makefiles use some GNU extensions, so a basic POSIX make will not work. Linux systems typically come with a satisfactory make. BSD based systems (i.e., NetBSD, FreeBSD) typically have GNU make as the gmake program.  * **GNU Make**\\ The Makefiles use some GNU extensions, so a basic POSIX make will not work. Linux systems typically come with a satisfactory make. BSD based systems (i.e., NetBSD, FreeBSD) typically have GNU make as the gmake program.
  
- * **ISO C++ Compiler**\\ The ivl and ivlpp programs are written in C++ and make use of templates and some of the standard C++ library. egcs and recent gcc compilers with the associated libstdc++ are known to work. MSVC++ 5 and 6 are known to definitely *not* work.+ * **ISO C++ Compiler**\\ The ''​ivl'' ​and ''​ivlpp'' ​programs are written in C++ and make use of templates and some of the standard C++ library. egcs and recent gcc compilers with the associated libstdc++ are known to work. MSVC++ 5 and 6 are known to definitely *not* work.
  
  * **bison and flex**  * **bison and flex**
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  * **gperf 2.7**\\ The lexical analyzer doesn'​t recognize keywords directly, but instead matches symbols and looks them up in a hash table in order to get the proper lexical code. The gperf program generates the lookup table.\\ A version problem with this program is the most common cause of difficulty. See the Icarus Verilog FAQ.  * **gperf 2.7**\\ The lexical analyzer doesn'​t recognize keywords directly, but instead matches symbols and looks them up in a hash table in order to get the proper lexical code. The gperf program generates the lookup table.\\ A version problem with this program is the most common cause of difficulty. See the Icarus Verilog FAQ.
  
- * **readline 4.2**\\ On Linux systems, this usually means the readline-devel rpm. In any case, it is the development headers of readline that are needed.+ * **readline 4.2**\\ On Linux systems, this usually means the ''​readline-devel'' ​rpm. In any case, it is the development headers of readline that are needed.
  
  * **termcap**\\ The readline library in turn uses termcap.  * **termcap**\\ The readline library in turn uses termcap.
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 the configure scripts. the configure scripts.
  
- * **autoconf 2.53**\\ This generates configure scripts from configure.in. The 2.53 or later versions are known to work, autoconf 2.13 is reported to *not* work.+ * **autoconf 2.53**\\ This generates configure scripts from ''​configure.in''​. The 2.53 or later versions are known to work, autoconf 2.13 is reported to *not* work.
  
 ==== Compilation ==== ==== Compilation ====
  
-Unpack the tar-ball and cd into the verilog-#########​ directory +Unpack the tar-ball and cd into the ''​verilog-#########​'' ​directory and compile the source
-(presumably that is how you got to this README) ​and compile the source+
 with the commands: with the commands:
  
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 ==== Preprocessing ==== ==== Preprocessing ====
  
-There is a separate program, ivlpp, that does the preprocessing. This +There is a separate program, ​''​ivlpp''​, that does the preprocessing. This 
-program implements the `include and `define directives producing+program implements the ''​`include'' ​and ''​`define'' ​directives producing
 output that is equivalent but without the directives. The output is a output that is equivalent but without the directives. The output is a
 single file with line number directives, so that the actual compiler single file with line number directives, so that the actual compiler
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 One can see a human readable version of the final pform by using the One can see a human readable version of the final pform by using the
-''​-P <​path>''​ flag to the ''​ivl''​ subcommand. This will cause ivl+''​-P <​path>''​ flag to the ''​ivl''​ subcommand. This will cause ''​ivl''​
 to dump the pform into the file named ''<​path>''​. (Note that this is not to dump the pform into the file named ''<​path>''​. (Note that this is not
 normally done, unless debugging the ''​ivl''​ subcommand.) normally done, unless debugging the ''​ivl''​ subcommand.)
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 includes all the behavioral descriptions,​ as well as gates and wires. includes all the behavioral descriptions,​ as well as gates and wires.
  
-The elaborate() function performs the elaboration.+The ''​elaborate()'' ​function performs the elaboration.
  
 One can see a human readable version of the final, elaborated and One can see a human readable version of the final, elaborated and
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 This pass scans through the pform looking for scopes and parameters. A This pass scans through the pform looking for scopes and parameters. A
-tree of NetScope objects is built up and placed in the Design object, +tree of ''​NetScope'' ​objects is built up and placed in the ''​Design'' ​object, 
-with the root module represented by the root NetScope object. The+with the root module represented by the root ''​NetScope'' ​object. The
 ''​elab_scope.cc''​ file contains most of the code for handling this phase. ''​elab_scope.cc''​ file contains most of the code for handling this phase.
  
-The tail of the elaborate_scope behavior (after the pform is +The tail of the ''​elaborate_scope'' ​behavior (after the pform is 
-traversed) includes a scan of the NetScope tree to locate defparam+traversed) includes a scan of the ''​NetScope'' ​tree to locate defparam
 assignments that were collected during scope elaboration. This is when assignments that were collected during scope elaboration. This is when
 the defparam overrides are applied to the parameters. the defparam overrides are applied to the parameters.
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 === Netlist Elaboration === === Netlist Elaboration ===
  
-After the scopes and parameters are generated and the NetScope tree+After the scopes and parameters are generated and the ''​NetScope'' ​tree
 fully formed, the elaboration runs through the pform again, this time fully formed, the elaboration runs through the pform again, this time
 generating the structural and behavioral netlist. Parameters are generating the structural and behavioral netlist. Parameters are
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  * constant propagation  * constant propagation
  
-The actual functions performed are specified on the ivl command line by+The actual functions performed are specified on the ''​ivl'' ​command line by
 the ''​-F''​ flags (see below). the ''​-F''​ flags (see below).
  
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 </​note>​ </​note>​
  
-The parser accepts, as an extension to Verilog, the $attribute module +The parser accepts, as an extension to Verilog, the ''​$attribute'' ​module 
-item. The syntax of the $attribute item is:+item. The syntax of the ''​$attribute'' ​item is:
  
  $attribute (<​identifier>,​ <​key>,​ <​value>​);​  $attribute (<​identifier>,​ <​key>,​ <​value>​);​
  
-The $attribute keyword looks like a system task invocation. The+The ''​$attribute'' ​keyword looks like a system task invocation. The
 difference here is that the parameters are more restricted than those difference here is that the parameters are more restricted than those
-of a system task. The <​identifier>​ must be an identifier. This will be +of a system task. The ''​<​identifier>​'' ​must be an identifier. This will be 
-the item to get an attribute. The <key> and <​value>​ are strings, not+the item to get an attribute. The ''​<key>'' ​and ''​<​value>​'' ​are strings, not
 expressions,​ that give the key and the value of the attribute to be expressions,​ that give the key and the value of the attribute to be
 attached to the identified object. attached to the identified object.
  
-Attributes are [<​key>​ <​value>​] pairs and are used to communicate with+Attributes are ''​[<​key>​ <​value>​]'' ​pairs and are used to communicate with
 the various processing steps. See the documentation for the processing the various processing steps. See the documentation for the processing
 step for a list of the pertinent attributes. step for a list of the pertinent attributes.
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 Attributes can also be applied to gate types. When this is done, the Attributes can also be applied to gate types. When this is done, the
 attribute is given to every instantiation of the primitive. The syntax attribute is given to every instantiation of the primitive. The syntax
-for the attribute statement is the same, except that the <​identifier>​+for the attribute statement is the same, except that the ''​<​identifier>​''​
 names a primitive earlier in the compilation unit and the statement is names a primitive earlier in the compilation unit and the statement is
 placed in global scope, instead of within a module. The semicolon is placed in global scope, instead of within a module. The semicolon is
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 Icarus Verilog also accepts the Verilog 2001 syntax for Icarus Verilog also accepts the Verilog 2001 syntax for
-attributes. They have the same general meaning as with the $attribute+attributes. They have the same general meaning as with the ''​$attribute''​
 syntax, but they are attached to objects by position instead of by syntax, but they are attached to objects by position instead of by
 name. Also, the key is a Verilog identifier instead of a string. name. Also, the key is a Verilog identifier instead of a string.
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 ===== Running iverilog ===== ===== Running iverilog =====
  
-The preferred way to invoke the compiler is with the iverilog(1) +The preferred way to invoke the compiler is with the ''​iverilog(1)''​ 
-command. This program invokes the preprocessor (ivlpp) and the +command. This program invokes the preprocessor (''​ivlpp''​) and the 
-compiler (ivl) with the proper command line options to get the job +compiler (''​ivl''​) with the proper command line options to get the job 
-done in a friendly way. See the iverilog(1) man page for usage details.+done in a friendly way. See the ''​[[icarus_mp|iverilog(1)]]'' ​man page for usage details.
  
  
 ==== Examples ==== ==== Examples ====
  
-Example: Compiling ​"hello.vl"+Example: Compiling ​''​hello.vl''​
  
------------------------- ​hello.vl ​----------------------------+<code verilog "hello.vl">
 module main(); module main();
  
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 endmodule endmodule
 +</​code>​
  
--------------------------------------------------------------- +Ensure that ''​iverilog'' ​is on your search path, and the ''​vpi'' ​library
- +
-Ensure that "iverilog" ​is on your search path, and the vpi library+
 is available. is available.
  
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   iverilog hello.vl   iverilog hello.vl
  
-(The above presumes that /​usr/​local/​include and /​usr/​local/​lib are+(The above presumes that ''​/​usr/​local/​include'' ​and ''​/​usr/​local/​lib'' ​are
 part of the compiler search path, which is usually the case for gcc.) part of the compiler search path, which is usually the case for gcc.)
  
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   ./a.out   ./a.out
  
-You can use the "-o" ​switch to name the output command to be generated +You can use the ''​-o'' ​switch to name the output command to be generated 
-by the compiler. See the iverilog(1) man page.+by the compiler. See the ''​[[icarus_mp|iverilog(1)]]'' ​man page.
  
 ===== Unsupported Constructs ===== ===== Unsupported Constructs =====
  
-Icarus Verilog is in development - as such it still only supports a+Icarus Verilog is in development---as such it still only supports a
 (growing) subset of Verilog. ​ Below is a description of some of the (growing) subset of Verilog. ​ Below is a description of some of the
 currently unsupported Verilog features. This list is not exhaustive, currently unsupported Verilog features. This list is not exhaustive,
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 constructs. constructs.
  
-  ​System functions are supported, but the return value is a little +  ​System functions are supported, but the return value is a little tricky. See SYSTEM FUNCTION TABLE FILES in the [[icarus_mp|iverilog man page]].
-    ​tricky. See SYSTEM FUNCTION TABLE FILES in the iverilog man page.+
  
-  ​Specify blocks are parsed but ignored in general.+  ​Specify blocks are parsed but ignored in general.
  
-  ​trireg is not supported. tri0 and tri1 are supported.+  ​* ''​trireg'' ​is not supported. ​''​tri0'' ​and ''​tri1'' ​are supported.
  
-  ​tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1 +  ​tran primitives, i.e. ''​tran''​''​tranif1''​''​tranif0''​''​rtran''​''​rtranif1'' ​and ''​rtranif0'' ​are not supported.
-    ​and rtranif0 are not supported.+
  
-  ​Net delays, of the form "wire #N foo;" ​do not work. Delays in +  ​Net delays, of the form ''​wire #N foo;'' ​do not work. Delays in every other context do work properly, including the V2001 form ''​wire #5 foo = bar;''​
-    ​every other context do work properly, including the V2001 form +
-    "wire #5 foo = bar;"+
  
-  ​Event controls inside non-blocking assignments are not supported. +  ​Event controls inside non-blocking assignments are not supported. i.e.: ''​a <= @(posedge clk) b;''​
-    ​i.e.: a <= @(posedge clk) b;+
  
-  ​Macro arguments are not supported. `define macros are supported, +  ​Macro arguments are not supported. ​''​`define'' ​macros are supported, but they cannot take arguments.
-    ​but they cannot take arguments.+
  
 ==== Nonstandard Constructs or Behaviors ==== ==== Nonstandard Constructs or Behaviors ====
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 IEEE1364 standard, but have well defined meaning, and also sometimes IEEE1364 standard, but have well defined meaning, and also sometimes
 gives nonstandard (but extended) meanings to some features of the gives nonstandard (but extended) meanings to some features of the
-language that are defined. See the "extensions.txt" ​documentation for+language that are defined. See the ''​extensions.txt'' ​documentation for
 more details. more details.
  
 +<​code>​
     $is_signed(<​expr>​)     $is_signed(<​expr>​)
  This system function returns 1 if the expression contained is  This system function returns 1 if the expression contained is
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  -g2 flag to iverilog, and turned on explicitly with the -g2x  -g2 flag to iverilog, and turned on explicitly with the -g2x
  flag to iverilog.  flag to iverilog.
 +</​code>​
  
 ===== Credits ===== ===== Credits =====
  
-Except where otherwise noted, Icarus Verilog, ivl and ivlpp are+Except where otherwise noted, Icarus Verilog, ​''​ivl'' ​and ''​ivlpp'' ​are
 Copyright Stephen Williams. The proper notices are in the head of each Copyright Stephen Williams. The proper notices are in the head of each
 file. However, I have early on received aid in the form of fixes, file. However, I have early on received aid in the form of fixes,
geda/icarus_readme.txt · Last modified: 2014/04/14 09:57 by rlutz