geda:master_attributes_list
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| Both sides previous revision Previous revision Next revision | Previous revision Last revision Both sides next revision | ||
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geda:master_attributes_list [2017/11/15 22:33] newell [pinseq] |
geda:master_attributes_list [2017/11/15 22:34] newell [refdes] |
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| ==== pintype ==== | ==== pintype ==== | ||
| - | Each pin must have a **pintype**=value attribute attached to it and should be make hidden. Table 1 shows valid values for this attribute.\\ | + | Each pin must have a **pintype**=value attribute attached to it and should be made hidden. Table 1 shows valid values for this attribute.\\ |
| This attribute is not used extensively in the symbol library, but it will be used for DRC and netlisting. Use "Passive" if no other type matches.\\ | This attribute is not used extensively in the symbol library, but it will be used for DRC and netlisting. Use "Passive" if no other type matches.\\ | ||
| //Examples://\\ ''pintype=clk''\\ ''pintype=in''\\ ''pintype=pas'' | //Examples://\\ ''pintype=clk''\\ ''pintype=in''\\ ''pintype=pas'' | ||
| Line 131: | Line 131: | ||
| * No hyphens. This might upset the M4 macro language potentially used to generate footprints. "_" is ok. | * No hyphens. This might upset the M4 macro language potentially used to generate footprints. "_" is ok. | ||
| * Any lower case suffix is ignored. This is so you can, place four discrete NAND gates on the schematic called U1a, U1b, U1c and U1d. They will netlist into a single footprint named U1. | * Any lower case suffix is ignored. This is so you can, place four discrete NAND gates on the schematic called U1a, U1b, U1c and U1d. They will netlist into a single footprint named U1. | ||
| - | * Non-ASCII characters like like üöäß will not print in pcb | + | * Non-ASCII characters like üöäß will not print in pcb |
geda/master_attributes_list.txt · Last modified: 2017/11/15 22:36 by newell
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