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+====== Verilog netlister README ======
+<code>Verilog netlister readme.
+THIS IS FREE SOFTWARE, see the included file COPYING for more info.
+Latest README:
+	This is the fifth release of the Verilog netlister for gEDA.
+	New in this release:
+) Escaped Verilog identifiers.
+	To facilitate board level simulations, the Verilog netlister now
+outputs `escaped' Verilog identifiers for any net, port or instance name
+that does not appear to be a valid Verilog identifier.  In this way,
+chips with numbered pins can be netlisted and models constructed to run
+digital simulations of complete circuits.
+		Mike Jarabek
+----- OLDER README.verilog's -----
+	This is the fourth release of the Verilog netlister for gEDA.
+	New in this release:
+) Multiple width wires.
+How to use: (mostly taken from a previous readme... )
+       Here's how to proceed to make a schematic that can be netlisted
+to verilog.
+) Create your modules by the standard method, keep in mind
+              that you must supply a `pin#' attribute for each port
+              you want to create in the generated verilog.  gmk_sym is
+              useful for this.
+) Place each of your newly created modules on the
+              schematic.  You may also place primitives from the
+              `verilog' symbol library.  Be sure to give a _unique_
+              `uref' to every symbol you place on the schematic,
+              unless two symbols are actually different parts of the
+              same module, and the pins listed on each symbol do not
+              have any names in common.  Otherwise they will not get
+              netlisted.
+) Connect nets between the modules you want.  Remember, if
+              you want legible Verilog later, don't forget to name all
+              your nets by attaching `label' attributes to them.  For
+              Multiple bit wires just use standard Verilog notation.
+              The netlister will figure out which bit ordering you
+              want.  Be sure to have at least one net labeled with the
+              complete range expression, otherwise the netlister will
+              guess at whether you wanted net[15:0] or net[0:15] in
+              your declarations.  Any inconsistent ranges will be
+              reported as a warning.  Strings that appear to be
+              invalid Verilog identifiers will be printed with a
+              warning, but otherwise ignored. (If you get a warning
+              for a valid Verilog identifier, please post a bug
+              report!)
+) Insert IPAD's, OPAD's, and IOPAD's for all the nets you
+              want to be visible in the module declaration statement.
+              It is especially important to make sure that the nets
+              you hook up to the pads are named, as the net names
+              could change from run to run, that's a bad thing. (I/O
+              pads would be a good place to put the aformentionned
+              full range expressions.  Range expressions on I/O pads
+              are ignored when outputting the module declaration, but
+              they are used in figuring out the final bit ranges.)
+              Every pad must have a unique uref, otherwise the
+              netlister will get confused.
+) Add an unattached attribute `module_name=Your_Module'
+	      somewhere on the schematic, near the title block is
+	      good.  This will name the generated Verilog module
+	      `Your_Module'.
+) Save your design.
+) Run the schematic through the netlister:
+		  gnetlist -g verilog -o output.v schematic.sch
+a) Check the output for correctness, _especially_ if you got
+               any warnings. (There should be no warnings.)
+) Feed the netlist to your favorite simulator/synthesis tool.
+					Mike Jarabek
+        This is the third release of the Verilog netlister for geda.
+        Fixed in this release:
+) Netlister no longer barfs if there are no
+           Input/Output/InOut ports on the module.
+) Module instantiation code much improved/cleaned up, mostly
+           due to g_netlist.c patch.
+        New in this release:
+) A whole wack-load of symbols, I created a C program that
+           generates n-input versions of and, nand, or, nor, xor, and
+           xnor symbols
+) Modules instantiated with positional port connections.
+           Just add the attribute `VERILOG_PORTS=POSITIONAL' to your
+          symbol file as an unattached attribute, or attach it to the
+           symbol on the schematic.
+) Added bufif?, notif?, not and buf symbols.
+) Added example of positional port module instantiation to
+           the example schematic
+) Added 7447 example schematic
+        Coming:
+) Module instantiation parameters. (probably by an attribute)
+        Included in this tar-ball are three patch files against the
+        19990705 version of gEDA.  Apply g_netlist.c.diff and
+        g_register.c.diff to the files in gnetlist/src/ and
+        gnetlist.scm.diff to gnetlist.scm in the gnetlist/scheme
+        directory. You may have to regenerate prototype.h, or manually
+        patch it. Replace the symbols in the sym/verilog directory
+        with the symbols in this distribution. (I have modified all of
+        the symbols to use the new unattached attribute convention for
+        device et al.) (if you have applied the patch I sent to the
+        mailing list that fixes netlisting a module with no ports, you
+        may have trouble applying the gnetlist.scm.diff patch.) Don't
+        forget to do a `make all install' after applying the patches.
+	Once again, to netlist the example schematics to verilog type:
+        (Assuming gnetlist has been patched and is properly installed.)
+        gnetlist -g verilog -o test.v examples/sch/test.sch
+        or
+        gnetlist -g verilog -o 7447.v examples/sch/7447.sch
+(This README was from 19990629)
+Verilog netlister readme.
+THIS IS FREE SOFTWARE, see the included file COPYING for more info.
+	This is the second release of the Verilog netlister for geda.
+	Fixed in this release:
+) The last comma in the argument list to instantiations and
+           module definitions is now suppressed
+) Better handling of `special' components has been added
+	New in this release:
+) Continuous assignments to 1'b0 and 1'b1 can now be
+           generated by connecting the `high' or `low' symbol to a
+           net.
+				Mike Jarabek
+				mjarabek@playground.net
+--
+	This the verilog netlister for gEDA.  Included in the tarball
+are several diff files against the 19990327 gEDA distribution.  All of
+the patches apply to the gnetlist subirectory.  You should be able to
+apply them with `patch -p1'.
+      The netlister has its limitations:  (most of these will
+eventually get fixed, I hope..)
+) Components connected by reference, (i.e. by having named
+              net stubs attached to pins, but not conected by a
+              continuous line) create duplicate entries in the wire
+              declaration section of the verilog code.
+) Multiple width wires don't work.  (Busses will help
+              this)
+) There is no way to force a signal to 1,0,z,x (yet).
+) Some scheme code needs to be improved. (Mainly the
+              classification code, it inserts `()' elements into the
+              output lists. (I should know how to fix this in a day or
+              two.. too bad I never got a scheme course before..))
+) I don't know if this will work on multiple page schematics.
+) The top level module is outputted with the same name
+              every time, I don't currently think there is a way to
+              get at the name of the top level schematic.
+      The netlister does some neat things:
+) It outputs a verilog module with proper port
+              declarations, outputs are declared as outputs, inputs
+              are declared as inputs, and bidirectional signals are
+              declared as inouts.
+) All nets that are found on the design are declared as
+              wires. (This is to allow for net attributes later to
+              declare wand's and such)
+) Any components placed on the schematic that are given
+              uref attributes create a verilog instantiation for the
+              name of the module as stored in the `device' attribute,
+              the instatiated name is given as the `uref' attribute.
+) All connections into and out of instantiated modules are
+              made by name, and not by order, because I can't be sure
+              that the order will be right coming off the schematic.
+              (anyway, that's better for the long run.)
+) A comment is inserted at the top of the module to say
+              that the file was automatically generated.
+       Here's how to proceed to make a schematic that can be netlisted
+to verilog.
+) Create your modules by the standard method, keep in mind
+              that you must supply a `pin#' attribute for each port
+              you want to create in the generated verilog.  gmk_sym is
+              useful for this (with the patch to allow ascii pin names).
+) Place each of your newly created modules on the
+              schematic
+) Connect nets between the modules you want.  Remember, if
+              you want legible verilog later, don't forget to name all
+              your nets by attaching `label' attributes to them.
+) Insert IPAD's, OPAD's, and IOPAD's for all the nets you
+              want to be visible in the module declaration statement.
+              It is especially important to make sure that the nets
+              you hook up to the pads are named, as the net names
+              could change from run to run, that's a bad thing.
+) Save your design.
+) Run the schematic through the netlister:
+		  gnetlist -g verilog -o output.v schematic.sch
+a) Edit the output file to have the right module name, and
+               to remove any duplicate wires.
+    There is an example schematic in the schematic directory, and a
+    copy of the verilog netlist generated.
+The mechanics:
+    The I/O ports for the module are detected by enumerating all of
+    the nets attached to any symbol bearing the device name of `IPAD',
+    `OPAD', or `IOPAD'.  If you name one of your blocks with that
+    name, don't be surprised if you find `extra' ports in the module
+    declaration.
+    The wires are declared by walking through the list of nets
+    returned by the function that I patched into gnetlist.  This is
+    the source of the duplicate wire declarations.  This should
+    probably get fixed when `net_is_duplicate' gets set for
+    connections made by reference.
+    Module instantiations are created by enumerating the pins found on
+    a symbol and connecting the nets found to the pins.  If your block
+    has spelling errors, then the module instantiation won't work.
+    You will have to manually trace back to find the error.
+				Mike Jarabek
+------------ Below is the previous version README -------------------
+Verilog netlister readme.
+THIS IS FREE SOFTWARE, see the included file COPYING for more info.
+	This the verilog netlister for gEDA.  Included in the tarball
+are several diff files against the 19990327 gEDA distribution.  All of
+the patches apply to the gnetlist subirectory.  You should be able to
+apply them with `patch -p1'.
+[ editor's note, if you are reading this file in a gEDA dist, then all
+  the required patching and integration is already done ]
+      The netlister has its limitations:  (most of these will
+eventually get fixed, I hope..)
+) Components connected by reference, (i.e. by having named
+              net stubs attached to pins, but not conected by a
+              continuous line) create duplicate entries in the wire
+              declaration section of the verilog code.
+) Multiple width wires don't work.  (Busses will help
+              this)
+) There is no way to force a signal to 1,0,z,x (yet).
+) Some scheme code needs to be improved. (Mainly the
+              classification code, it inserts `()' elements into the
+              output lists. (I should know how to fix this in a day or
+              two.. too bad I never got a scheme course before..))
+) I don't know if this will work on multiple page schematics.
+) The top level module is outputted with the same name
+              every time, I don't currently think there is a way to
+              get at the name of the top level schematic.
+      The netlister does some neat things:
+) It outputs a verilog module with proper port
+              declarations, outputs are declared as outputs, inputs
+              are declared as inputs, and bidirectional signals are
+              declared as inouts.
+) All nets that are found on the design are declared as
+              wires. (This is to allow for net attributes later to
+              declare wand's and such)
+) Any components placed on the schematic that are given
+              uref attributes create a verilog instantiation for the
+              name of the module as stored in the `device' attribute,
+              the instatiated name is given as the `uref' attribute.
+) All connections into and out of instantiated modules are
+              made by name, and not by order, because I can't be sure
+              that the order will be right coming off the schematic.
+              (anyway, that's better for the long run.)
+) A comment is inserted at the top of the module to say
+              that the file was automatically generated.
+       Here's how to proceed to make a schematic that can be netlisted
+to verilog.
+) Create your modules by the standard method, keep in mind
+              that you must supply a `pin#' attribute for each port
+              you want to create in the generated verilog.  gmk_sym is
+              useful for this (with the patch to allow ascii pin names).
+) Place each of your newly created modules on the
+              schematic
+) Connect nets between the modules you want.  Remember, if
+              you want legible verilog later, don't forget to name all
+              your nets by attaching `label' attributes to them.
+) Insert IPAD's, OPAD's, and IOPAD's for all the nets you
+              want to be visible in the module declaration statement.
+              It is especially important to make sure that the nets
+              you hook up to the pads are named, as the net names
+              could change from run to run, that's a bad thing.
+) Save your design.
+) Run the schematic through the netlister:
+		  gnetlist -g verilog -o output.v schematic.sch
+a) Edit the output file to have the right module name, and
+               to remove any duplicate wires.
+    There is an example schematic in the schematic directory, and a
+    copy of the verilog netlist generated.
+The mechanics:
+    The I/O ports for the module are detected by enumerating all of
+    the nets attached to any symbol bearing the device name of `IPAD',
+    `OPAD', or `IOPAD'.  If you name one of your blocks with that
+    name, don't be surprised if you find `extra' ports in the module
+    declaration.
+    The wires are declared by walking through the list of nets
+    returned by the function that I patched into gnetlist.  This is
+    the source of the duplicate wire declarations.  This should
+    probably get fixed when `net_is_duplicate' gets set for
+    connections made by reference.
+    Module instantiations are created by enumerating the pins found on
+    a symbol and connecting the nets found to the pins.  If your block
+    has spelling errors, then the module instantiation won't work.
+    You will have to manually trace back to find the error.
+				Mike Jarabek
+</code>

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