geda:hierarchy
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geda:hierarchy [2015/03/28 17:02] rlutz More work on the page |
geda:hierarchy [2016/02/29 09:10] rlutz start writing section on netname=/net= mangling |
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| ===== Separating net=/netname= namespaces ===== | ===== Separating net=/netname= namespaces ===== | ||
| - | … | + | The typical and cleanest way to use hierarchy is to enable both refdes and net=/netname= mangling. This means that the subcircuit lives in a namespace of its own, and the only way to connect nets between the instantiating and the instantiated schematic is through pins of the subsheet symbol and I/O ports in its schematic. If you want to include a subcircuit multiple times in your design, even though it's not strictly necessary, this is the recommended way to use hierarchy, as you would otherwise have to be very careful about avoiding naming nets in the subschematic which would cause them to be silently short-circuited between instantiations. |
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| + | ==== netname= mangling vs. net= mangling ==== | ||
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| + | There are two slightly different options which influence net namespaces: ''netname='' mangling means that net names set via the ''netname='' attribute on nets are prefixed or suffixed with the subsheet instance's hierarchy tag. ''net='' attribute mangling means that net names which are set via the ''net='' attribute on components (like, for example, ''Vcc'' and ''GND'' pins in some libraries) are prefixed or suffixed with the subsheet instance's hierarchy tag. | ||
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| + | Usually, when using net namespaces, you would enable both ''netname='' and ''net='' mangling. Depending on how you use hierarchy in your design, there might be use cases where you might want to disable one of them, though: If you disable ''netname='' mangling, you gain the ability to use global net names and connect nets across the hierarchy by setting the ''netname='' attribute while still having implicit nets separate. If you disable ''net='' mangling, all implicit pins (usually power and ground pins) across all of your schematic pages will be connected, so you don't have to use explicit power and ground pins on your subsheet symbols. Both approaches come at the cost of reduced readability, though: you can't tell any more how a subsheet is connected to the rest of the design by just looking at the schematic. | ||
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geda/hierarchy.txt · Last modified: 2016/02/29 09:42 by rlutz
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