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This page will serve to document the design rule checker. This is presently documented "as-is".

For work tasks, see the [[https://blueprints.launchpad.net/pcb/+spec/drc|LaunchPad blueprint]].

The DRC code makes extensive use of the [[pcb:connection_lookup | "connection lookup"]] code.

=====DRC Violations=====
  * Line/arc/silk width is too thin
  * Pin/via annular ring too small
  * Pin/via drill size too small
  * Pad too thin
  * Silk lines in elements
  * No paste
  * Insufficient copper overlap
  * Insufficient copper spacing
  * Hole too close to line/pad/pin/via
  * Hole touches arc
  * Insufficient clearance inside polygon
  * Joined line not connected to polygon

=====Process=====
Presently, the violations are identified in find.c, and then appended to a list in the gtk hid. In the lesstif and batch hids, you get a pop-up window or a text prompt that describes the error.

Executing the DRC() action will wipe out the selected, found, and DRC flags on most objects, although, apparently not elements.

  - Execute the DRC() action.
  - Generate the "DRC doesn't catch everything" warning.
  - Save layer state and turn on all layers.
  - Clear the FOUNDFLAG, DRCFLAG, and SELECTEDFLAG on all objects. DRC uses these flags to find errors. After clearing all the flags, the undo serial number is incremented. When we're done, we'll clear all the flags again, and execute an "undo" to restore the state.
  - InitConnectionLookup -- This resets all of the lists that are used for building the connectivity map.
  - Use DRCFind to check for "insufficient overlap" and "insufficient clearance" in copper objects.
    - For every element pin, pad, and via, execute DRCFind. DRCFind builds a connection list starting from the given pin/pad/via four times using the [[pcb:connection_lookup | "connection lookup"]] code.
    - Check for insufficient overlap:
      - Apply a global bloat of value "Shrink", and build a connection list, with global drc set to false. This will set the DRCFLAG and SELECTEDFLAG on every object that is touching the given pin/pad/via.
      - Apply a global bloat of value 0, and build a connection list with global "drc" set to true.
      - With "drc" set to true, the add_object_to_list function will exit with a return status when it finds something that doesn't have the SELECTEDFLAG set. "Thing" is set to the new object.
      - This status propagates back up, and the connection lookup is terminated early.
      - A drc_violation is created that includes the "Thing" object.
    - Check for insufficient clearance:
      - Do the same routine as above, except starting with a global bloat of 0, and using a bloat of "Bloat" for the second run through.
  - Check for minimum copper line widths:
    - Iterate over all copper lines with COPPERLINE_LOOP
    - Test the thickness value of the line
    - Generate a drc_violation if the thickness is too thin.
    - Iterate over all copper arcs with COPPERARC_LOOP
    - ditto
  - Check pin annular rings
  - Check drill sizes
  - Check pad widths
  - Check via annular rings
  - Check via drill sizes
  - Check silk line widths
  - Check element silk line widths
  - Restore the layer stack visibility
  - return the number of violations found
  
=====To Do List=====
====DRC tests====
  * Go through the DRC code for different kinds of violations to check that all possible code paths are being tested
  * Review the DRC tests and check that the results are correct!
  * Generate graphical output for the DRC report
  * Generate LaTeX output for the DRC report (wishlist!)
  * Figure out what else uses the "ConnectionLookup" code and write tests so that we don't break anything else as we're reworking the DRC
===Additional test cases===
As I work through the code, I'm going to jot some things down here regarding tests that ought to be done. Much of this stuff tests the more general geometry code too, so, maybe two birds with one stone.

  * Square pads \\ In lots of cases, square pads are handled differently than ones with round ends, so, square pads should definitely be tested.
  * Polygon clearance \\ Some of the polygon clearance tests aren't working as intended. The clearance to inner and outer edges isn't tested right because those objects aren't connected to pins. The copper-areas-too-close violations are found using DRCFind, which only starts at pins, pads, and vias. Also, once one of the violations was detected, depending on where it started, if it flags the polygon, it may not report further violations to the polygon.

====DRC backend work====
  * Separate the DRC code from the "ConnectionLookup" code.
  * Get rid of the "drc", "User", and "AndDraw" parameters. (Still trying to figure out what the implications of this would be)
  * Factor all of the different DRC tests into separate functions so that they can be executed individually.
  * Have DRC functions operate on "DataType" objects so that you can selectively apply the DRC to, say, the objects in the buffer
  * Work through more of Peter C's work to see how much of it we should incorporate (home/cparker/peterc_drc, he has quite a bit of good stuff here, but I'd like to include it intelligently instead of just picking the commits.)

====DRC interface====
  * Create a DRC panel in the preferences window that allows for adjusting settings (possibly with image descriptions of the violations) and running specific tests individually
  * Figure out what the lesstif HID requirements are for the DRC code (it works differently, presenting violation by violation)

====DRC bugs====
  * Highlight both offending objects instead of just one^^^
  * Find more than one "insufficient overlap" or "insufficient gap" per pin/pad/via^^^
  * Check for duplicate DRC errors before appending a new one (can happen if more than one pin is connected to an object)
  * On MacOS the images in the DRC window of the GTK HID are garbled
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